Well… It seems that I have forgotten to add a few things to the ALU that should be part of it… oops…
ALU
The ALU is one of the core components of the CPU, responsible for computing both arithmetic and logic operations, such as ADD and AND. It is also used to compare two operands for branch operations like BEQ.
It has two buffered inputs $ A $ and $ B $, as well as a buffered output $ O $, as well as input for control signals to select the operations of the ALU, as well as controlling the input and output buffers.
Input $ A $ is directly connected to only the General Purpose registers, and uses a up-down shift register to latch the value, controlled by the $ AAE $ control signal to load the data, as well as the Carry flag $ CIn $ . Several control signals are used to control the Shift Register $ SHCLK $, $ SHDIR $ and $ SHCC $. Additionally the Carry Flag can be put into the ALU with the $ ACE $ signal.
Input $ B $ is connected to the Data Bus with a buffer D-latch controlled by the $ ABE $ control signal. $ B $ is only connected to the Bus, allowing it to take inputs from memory, as well as from the General Purpose Registers. This allows to reduce the difference between control operations between using inputs to operate on either memory or registers as the second input.
The output $ O $ is connected to a 2:1 multiplexer to select between the ALU output and the output of the Shift Register, with the $ OSEL $ Signal. It includes the Carry Flag $ COut $, as it is possible for both the ALU and the Shift Register to export a Carry Flag. The output from the Multiplexer is directly tied into the General Purpose Registers through ab buffer D-latch controlled by the $ AOE $ control signal. During branch operations, it is not active to transfer the output into the General Purpose Registers, but instead only changes the flags of the Flag Register.
Additionally fo the Carry Flag, the ALU and logic tied to it may create several flags, $ Z $, $ EQ $, $ N $ and $ OF $.
Possible Implementation
Originally it was the intention to design the ALU from scratch, however it was decided that it would be better to simply make use of existing 74 series TTL logic ICs for the ALU. If it is good enough for DEC to use on the PDP-11 and VAX workstation, it is good enough for the DWMC-16.
As such the ALU will be utilizing a set of 4 74181 4-bit arithmetic logic unit and function generator in combination with a single 74182 lookahead carry generator. For 74373 octal latch ICs will be used as input and output latches.
For the Shift Register, four 74194 4-bit bidirectional universal shift register will be used, with four 74157 2:1 Multiplexers for the output selection.
Finally, some logic will have to be used to support the shift register to allow rotation and shifting through Carry, as well as generating the Flags.
