DWMC-16 Design Part 5: Operations and OpCodes

This section contains a basic design of the DWMC-16 Operations and their OpCode design, meaning how operations are going to be represented in memory.

All operations share the same general OpCode Layout, consisting of a 6 bit OpCode, which allows for up to 64 different operations, followed by a 2 bit Operation Mode, which is needed to enable, for example, different memory addressing schemes, and finally an 8 bit Control Code, which in turn depends on the Operation Mode.

Generally, there are four different typed of operations:

• Data Transfer Operations
• Arithmetic Logical Operations
• Control Operations
• Other Operations

Data Transfer Operations

Data Transfer Operations are perhaps the most important operations within the DWMC-16 Instruction Set, as they are responsible for moving data between the memory and the CPU, as well as between registers. However, there are only three data transfer operations.

Internally, these operations are separated into two groups with LD and ST falling into the memory operations, while MOV is a register operation.

Memory Operations

The Memory Operations help define the different types of data access modes that will be used within the DWMC-16 Instruction Set by other operations, so the memory address modes will be defined in this subsection.

The general OpCode design has already been defined earlier and will be used here.

There are several different Address Modes encoded in the 2 bit Operation Mode and the four bit of the Control Code used by the ‘Other Modes’:

Register Mode

Register to Register Mode. This mode is not used by LD and ST, but almost exclusively by Arithmetic Logical Operations and Branch Operations.

Direct Mode

The Direct Mode loads the 16 bit value from the data word following the operation into the destination register.

Absolute Address Mode

This Mode uses the lower four bit [3:0] of the Control to encode the upper four bit [19:16] of the 20 bit address, while the data word following the operation encodes the lower 16 bit [15:0] of the 20 bit address. This allows to address the full memory space of the system.

Local Address Mode

The local address Mode allows to address only the local 64 kiWord address space, with the upper 4 bit [19:16] taken from the systems Program Counter.

PC Relative/Offset Mode

The relative/offset mode adds the content of the PC Offset Register to the Program Counter for addressing a memory cell. This can either be done by the register, or using a more direct method, where the command itself loads the data word following the operation directly into the PC Offset Register.

Index Y/Z Address Mode

In this addressing mode, the system uses the content of the Y/Z Index Register to point towards a memory cell to read data.

Offset y/Z Address Mode

Using this mode, the system is able to read from a list of data, relative to the address to the Y/Z Index Register, allowing access to lists/arrays of data. This can either be done by the register, or using a more direct method, where the command itself loads the data word following the operation directly into the Y/Z Offset Register.

Register Operation

There is only a single Register Operation, which is capable of moving data from a Source Register to a Destination Register, with the possibility of moving data between the two register pages.

Arithmetic Logical Operations

Arithmetic Logical Operations are operations that are done by the ALU of the DWMC-16 CPU. They are used to modify the data, and are able to read from memory directly, based around the Memory Modes defined under Data Transfer Operations.

There are two types of arithmetic logical operations, those with a single operand and those with two operands. INC, DEC, NOT, LLS/LRS and LLR/LRR are operations with one operand, while AND/ANDC, SUB/SUBC, AND/OR/XOR, and SB/RB are operations with two operands. In this SB/RB are slightly different and do not use the same opcode as the other two operand operations.

Single Operand

Single Operand Operations have a simple OpCode, where the Operation Mode is fixed to 00 and only the Destination Register is used.

Two Operands

The two Operand Operations are largely using the Memory Modes as defined under Data Transfer Operations. The only expectation are the SB/RB operations.

Control Operations

Control Operations are responsible for allowing the DWMC-16 CPU to make decisions based on data, and move around inside the code. Some of these operations can use the Memory Modes defined under Data Transfer Operations.

Again, there are two types of operations, conditional branch operations and unconditional jump operations.

Branch Operations

The six available branch operations are subdivided into two types, branch operations with a single operand BZ and BZI, as well as those with two operands BB, BE, BL and BLE.

To simplify the OpCode design, it is assumed that Branch operations are jumping to a relative address. This means that the branch target will remain within a 16 bit address window, allowing for a jump range of ±32 kiWord, using a signed 16 value.

Single Operand

Single Operand Branches are using just a single Source Register, which simplified their OpCode. Like in the Single Operand Arithmetic Logical Operations, the Operation Mode it set to 00, while the lowest four bit are set to 0000.

Two Operands

Much like the Two Operand Arithmetic Logical Operations the Two Operand Branch Operations make use of the Memory Modes defined under Data Transfer Operations, though they are extended by the one word of the value for the relative jump.

Unconditional Jumps

There are four available unconditional jump operations, which are once against subdivided into two types, jumps and returns, of which the jumps have a single operand, while the return operations have no operand, using the stack to get their return absolute address.

Jump Operations

Jump operations themselves make use of a modified version of the Memory Modes as defined under Data Transfer Operations. However, they do not make use of the Register or Direct Address Modes, and do not use a Destination Register.

Return Operations

The Return Operations do not use any operand and are therefore just a simple six bit opcode, followed by ten 0.

Other Operations

All operations that do not fit into the other three main types of operations, are listed in this section. None of these operations are making use of memory modes, but still are divided into two sub types.

The OpCodes Layout of these operations are simplified, with six bit opcodes, the Operation Mode set to 00 and the Control Code either set to 00000000 or set to contain the Source/Destination Register and the Stack (1, 2 or 3) used to contain the data. PUSH and POP are limited to the current Register Page and are not able to save any of the Special register to the selected Stack.

Memory Mode Mnemonics

Finally, there needs to be some thought put into the design of the Mnemonics used to designate the Memory Modes as defined under Data Transfer Operations for use in an Assembler program.