This section is about the design of the Memory System of the DWMC-16. It will discuss the Memory, the DMA Controller and the Memory Management Unit.
Memory
Internally, the memory of the DWMC-15 is 1 MiWord in size and split into 64 kiWord sectors, with eight sectors for the upper and lower memory each. Each sector is then subdivided into 16 4 kiWord blocks, though this is largely for the MMU, DMA and the OS to handle.
Of the the lower memory, the first three sectors are dedicated system RAM, mostly to be used by the systems OS, with the first 64 Words of the first sector used for te special use registers, interrupt vectors and the control registers for the DMA And MMU.
This if followed by one sector dedicated for the Mapped IO space, and finally four sectors for the BIOS and Main OS.
The upper eight sectors of memory are controlled in most part by the MMU, allowing to either swap out the entirety of the memory page or just single sectors. PS0 - PS3 signals are used to address a specific memory page.
Possible Implementation
For the lower memory, all memory can be placed on the same module, using an address decoder to access the memory ICs. It is likely that either two 62512 or four 62256 are used for each memory segment, while four SST39SF010A 128kx8 ICs might be used for the FLASH Memory. Using Flash Memory instead of EPROMs, allows to modify the BIOS and OS from inside the system. The rest is relatively simple address decoding that excludes the lowest 64 Words of memory.
The upper memory boards are likely to use the same 62512 or 62256 as the lower memory board, with some additional address decoding, with a dip switch dictating the page address.
Memory Management Unit
The Memory Management Unit is responsible for allowing the system to page out either the entirety of the upper memory page, single or multiple sectors or one or more blocks of memory.
To simplify and speed up the work of the Memory Management Unit, is is limited to a relatively simple design, which can swap up to eight sectors or blocks at once, however only do a single memory page.
Do do this, the MMU has eight Page Swap Registers $ PSR0-PSR7 $, which are set up to take the sector and block numbers that are to be swapped out, the swap mode and the target page to be swapped in. The swap is then activated by a single Swap Enable Flag $ SE $. To decide whether a page needs to be swapped out, the sector and block addresses in the Page Swap Register are compared to the upper seven address bytes of the address bus. If they are identical, the page address is set to the page select lines $ PS0-PS3 $.
The Swap Enable Flag of each Page Swap Register is resaved to the MMU Status Register as $ SEx $, allowing the OS to easily check whether a Page Swap Register is in use or not.
If any of the Page Swap Registers are set to Page Mode, with the $ PM $ flag in the MMU Status Register, the Page Registers are disabled and the page in the $ PM0-PM3 $ is used. If Segment mode is used, with the $ SM $ flag, any address in the Block flags are ignored. To enable Block mode, the $ BM $ Flag needs to be active.
Possible Implementation
To ensure that the MMU is as fast as possible, from a timing point of view, the MMU itself needs to be as shallow and simple as possible from a logic level. Which will influence the later logical design.
To Implement the Page Swap Registers, two 74373 octal latch ICs per register are used, with another for two for the MMU Status Register. as the comparator a single 74518 8-bit comparator used, with additional logic to enable/disable the Sector and Block selection.
Additional logic is needed to handle the MMU Status register to enable the use of a full page swap.
DMA Controller
The DMA controller takes care of moving data either between two places in memory, or between memory and an external IO device, without the CPU having to be involved. The DMA controller of the DWMC-16 has two channels with different duties.
Both DMA Channels share the same core functionality. They are taking in a source and a target address, as well as the size of the data block they are to copy and then use the address bus of the system when the CPU hands over the control with the use of the $ DMAE $ signal. The DMA Controller can signal back to the CPU that it hands back the address bus, when the $ DMAB $ falls back to low. The DMA can also request control over the bus with the $ DMAR $ signal. With the DMA Interrupt signal $ DMAI $, the DMA Controller can take control over the bus for a short time in Cycle Stealing Mode.
Common control flags are the Target/Source Page flags $ SP0-SP3 $ and $ TP0-TP3 $. The Channel Transfer Mode flag $ CTM0, CTM1 $ can be used to select between the two DMA controller modes:
Burst Mode The DMA takes over control of the address bus to transfer a larger block of data. Cycle Stealing Mode The DMA requests control over the bus with the \texttt{DMAI} signal, to transfer a word of data from a slow IO device, before returning control over the BUS back to the CPU. Interleaved Mod The DMA uses cycles when the CPU does not use the bus to transfer a block of data. This mode does not interfere with the use of the bus by the CPU at any time, but is a very slow method of data transfer.
DMA Channel 0 is specialised for moving data between an external IO device with a FIFO and memory. This IO device can either be an 8 bit or a 16 bit device, which is controlled by the Device Size Flag $ DS $. The Transfer Direction flag $ TD $ tells the Channel, whether the data is sent to or from an IO device. Depending on the transfer direction, either the target page or the source page is needed.
If DMA Channel 0 is in 8 bit mode, the DMA controller will read/write from the IO device twice, combining/splitting the data that is written/read from memory.
In operation, after each transfer of a data word the DMA Size Registers is decreased by one, while the DMA Source/Target Register is increased, depending on the Transfer Type.
DMA Channel 1 is responsible for moving up to entire Sector of memory either between sectors or between block of memory, which may or may not be on two different pages of the memory. For this, it does not need the Memory Management Unit, as the Channel has its own access to the Page Select lines $ PS0-PS3 $.
In operation, after each transfer of a data word the DMA Size Registers is decreased by one, while the DMA Source and Target Registers are increased.
Possible Implementation
For the Source, Target and Size Registers the use of 74191 synchronous presettable up/down 4-bit binary counter will be used, partially for a general uniformity over the systems design, as well as the need to increase and decrease the address bus via the DMA controller. For the Control Registers 74373 octal latches are more useful. The DMA Control Logic and other glue logic for addressing the registers, other logic ICs are needed, which are to be determined.
